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1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. 1.3 Absolute maximum ratings. 1/ Endurance: Device types 01-04, 09 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device types 05-08 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device types 10-13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply voltage range (VCC) 2/ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage temperature range (Tstg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum power dissipation (PD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . Junction temperature (TJ) 3/ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal resistance, junction-to-case (JC) (case outline X, Y) . . . . . . Thermal resistance, junction-to-case (JC) (case outlines T, Z) . . . . . . Thermal resistance, junction-to-case (JC) (case outline U) . . . . . . . . . Voltage on any pin with respect to ground 2/ . . . . . . . . . . . . . . . . . . . . . Voltage on pin A9 with respect to ground 4/ . . . . . . . . . . . . . . . . . . . . . VPP supply voltage with respect to ground 4/ . . . . . . . . . . . . . . . . . . . . VCC supply voltage with respect to ground 2/ . . . . . . . . . . . . . . . . . . . . Output short circuit current 5/ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Recommended operating conditions. 6/ Supply voltage range (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating temperature range (Tcase) . . . . . . . . . . . . . . . . . . . . . . . . . . . Low level input voltage range (VIL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High level input voltage range (VIH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . High level input voltage range, CMOS (VIH) . . . . . . . . . . . . . . . . . . . . . . Chip clear (VP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Digital logic testing for device classes Q and V. Fault coverage measurement of manufacturing logic tests (MIL-STD-883, test method 5012) . . . . . . . . . . . . . . . . . . . . 100 percent +4.5 V dc to +5.5 V dc -55C to +125C -0.5 V dc to +0.8 V dc +2.0 V dc to VCC +0.5 V dc VCC -0.5 V dc to VCC +0.5 V dc 11.4 V dc to 12.6 V dc
10,000 cycles/byte, minimum 1,000 cycles/byte, minimum 100,000 cycles/byte, minimum -2.0 V dc to +7.0 V dc -65C to +150C 1.0 W +300C +150C See MIL-STD-1835 13C/W 27C/W -2.0 V dc to +7.0 V dc -2.0 V dc to +13.5 V dc -2.0 V dc to +14.0 V dc -2.0 V dc to +7.0 V dc 200 mA 10 years minimum
1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Minimum dc voltage on input or VO pins is -0.5 V. During voltage transitions, inputs may overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum dc voltage on output and VO pins is VCC +0.5 V. During voltage transitions outputs may overshoot to VCC +2.0 V for periods up to 20 ns. 3/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883. 4/ Minimum dc input voltage on A9 or VPP may overshoot to +14.0 V for periods less than 20 ns. 5/ No more than one output shorted at a time. Duration of short circuit should not be greater than 1 second. 6/ All voltages are referenced to VSS (ground).
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2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the solicitation.
SPECIFICATION DEPARTMENT OF DEFENSE MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. STANDARDS DEPARTMENT OF DEFENSE MIL-STD-883 MIL-STD-973 MIL-STD-1835 HANDBOOKS DEPARTMENT OF DEFENSE MIL-HDBK-103 MIL-HDBK-780 List of Standard Microcircuit Drawings (SMD's). Standard Microcircuit Drawings. Test Method Standard Microcircuits. Configuration Management. Interface Standard for Microcircuit Case Outlines.
(Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094).
2.2 Non-Government publications. The following documents form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents which are DoD adopted are those listed in the issue of the DODISS cited in the solicitation. Unless otherwise specified, the issues of documents not listed in the DODISS are the issues of the documents cited in the solicitation.
AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM) ASTM Standard F1192-95 Standard Guide for the Measurement of Single Event Phenomena from Heavy Ion Irradiation of Semiconductor Devices.
(Applications for copies of ASTM publications should be addressed to the American Society for Testing and Materials, 1916 Race Street, Philadelphia, PA 19103). ELECTRONICS INDUSTRIES ASSOCIATION (EIA) JEDEC Standard EIA/JESD78 IC Latch-Up Test.
(Applications for copies should be addressed to the Electronics Industries Alliance, 2500 Wilson Blvd., Arlington, VA 22201.) (Non-Government standards and other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational services).
2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing shall take precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained.
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3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth tables. The truth tables shall be as specified on figure 3. 3.2.3.1 Unprogrammed devices. The truth table for unprogrammed devices for contracts involving no altered item drawing shall be as specified on figure 3 herein. When required, in screening (see 4.2 herein), or quality conformance inspection groups A, B, C, or D (see 4.4 herein), the devices shall be programmed by the manufacturer prior to test in a checkerboard or similar pattern (a minimum of 50 percent of the total number of bits programmed). 3.2.3.2 Programmed devices. The requirements for supplying programmed devices are not part of this document. 3.2.3.3 Command definitions. The command definitions table shall be as specified on figure 3. 3.2.4 Switching test circuits and waveforms. The switching test circuits and waveforms shall be as specified on figure 4. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked as listed in MIL-HDBK-103. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change as defined in MIL-STD-973.
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TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC +125C 1/ 4.5 V VCC 5.5 V unless otherwise specified Group A Subgroups Device type Min Limits Max Units
DC CHARACTERISTICS Input leakage current Output leakage current ILI VCC = VCC max, VIN = VCC max or VSS VCC = VCC max, VOUT = VCC max or VSS 1, 2, 3 All 1.0 A
ILO
1, 2, 3
All
10
A
VCC standby current (TTL) VCC standby current (CMOS) VCC active read current
ICCS1
VCC = VCC max, CE = VIH
CE = VCC 0.2 V,
VCC = VCC max VCC = VCC max, CE = VIL
IOUT = 0 mA, f = 6.0 MHz, OE = VIH
1, 2, 3
All
1.0
mA
ICCS2
1, 2, 3
All
100
A
ICC1
1, 2, 3
All
30
mA
VCC programming current VCC erase current VPP standby current
ICC2 ICC3
CE
= VIL, programming in progress CE = VIL, erasure in progress
1, 2, 3
All
30 2/
mA
1, 2, 3
All
30 2/
mA
IPPS
VPP = VPPL
1, 2, 3
All
10
A
VPP read current
IPP1
VPP = VPPH VPP = VPPL
1, 2, 3
All
200 10
A
VPP programming current
IPP2
VPP = VPPH, programming in progress
1, 2, 3
All
30 2/
mA
See footnotes at end of table.
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TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC +125C 1/ 4.5 V VCC 5.5 V unless otherwise specified Group A Subgroups Device type Min Limits Max Units
DC CHARACTERISTICS - Continued VPP erase current Low level input voltage High level input voltage (TTL) High level input voltage (CMOS) Low level output voltage High level output voltage (TTL) High level output voltage (CMOS) IPP3 VIL VPP = VPPH erasure in progress 1, 2, 3 1, 2, 3 All All -0.5 2/ 30 2/ 0.8 mA V
VIH1
1, 2, 3
All
2.0
VCC+ 0.5 2/
V
VIH2
1, 2, 3
All
0.7 VCC VCC+ 0.5 2/ 0.45
V
VOL
IOL = 2.1 mA, VCC = VCC min
1, 2, 3
All
V
VOH1
IOH = -2.5 mA, VCC = VCC min
1, 2, 3
All
2.4
V
VOH2 VOH3
IOH = -2.5 mA, VCC = VCC min IOH = -100 A, VCC = VCC min
1, 2, 3
All
0.85 VCC VCC- 0.4 2/
V V
A9 auto select voltage A9 auto select current VPP during read only operations VPP during read/write operations Functional tests
VID
A9 = VID
1, 2, 3
All
11.5
13.0
V
IID
A9 = VID max, VCC = VCC max
1, 2, 3
All
500 2/
A
VPPL
NOTE: erase/program are inhibited when VPP = VPPL
1, 2, 3
All
0
VCC+ 2.0 2/ 12.6
V
VPPH
1, 2, 3
All
11.4
V
See 4.4.1d
7, 8A, 8B
All
See footnotes at end of table.
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TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC +125C 1/ 4.5 V VCC 5.5 V unless otherwise specified Group A Subgroups Device type Min Limits Max Units
CAPACITANCE 2/ Input capacitance CIN1 VIN = 0 V, TA = 25C, f = 1.0 Mhz, see 4.4.1c 4 All 10 pF
Output capacitance
COUT
VOUT = 0 V, TA = 25C, f = 1.0 Mhz, see 4.4.1c VIN = 0 V, TA = 25C, f = 1.0 Mhz, see 4.4.1c
4
All
12
pF
VPP input capacitance CIN2
4
All
12
pF
AC CHARACTERISTICS - READ ONLY OPERATIONS (See figure 5 as applicable.) Read cycle time tAVAV 2/ 9, 10, 11 01,05,10 02,06,11 03,07,12 04,08,13 09 250 200 150 120 90 ns
Chip enable access time
tELQV
9, 10, 11
01,05,10 02,06,11 03,07,12 04,08,13 09 01,05,10 02,06,11 03,07,12 04,08,13 09
250 200 150 120 90 250 200 150 120 90
ns
Address access time
tAVQV
9, 10, 11
ns
See footnotes at end of table.
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TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC +125C 1/ 4.5 V VCC 5.5 V unless otherwise specified Group A Subgroups Device type Min Limits Max Units
AC CHARACTERISTICS - READ ONLY OPERATIONS - Continued. (See figure 5 as applicable.) Output enable access time tGLQV 9, 10, 11 01,05 02,06 03,07,10, 11,12 04,08,13 09 All 0 2/ 65 60 55 50 40 ns ns
Chip enable to output in low Z Chip disable to output in high Z Output enable to output in low Z Output disable to output in high Z
tELQX
9, 10, 11
tEHQZ
2/
9, 10, 11
All
55
ns
tGLQX
9, 10, 11
All
0 2/
ns
tGHQZ
2/
9, 10, 11
01,05 02,06 03,07,10, 11,12 04,08,09, 13 All 0 2/
60 45 35 30
ns
Output hold from address,
E , or C
OE

change Write recovery time before read
tAXQX
3/
9, 10, 11
ns
tWHGL
9, 10, 11
All
6.0
s
ERASE AND PROGRAMMING PERFORMANCE Chip erase Chip program Excludes 00H programming 9, 10, 11 All All 60 24 s s
Excludes system overhead 4/ 9, 10, 11
1/ Case temperatures are instant on. 2/ Parameters shall be tested as part of device initial characterization and after design and process change. Parameter shall be guaranteed to the limits specified in table I for all lots not specifically tested. 3/ Whichever occurs first. 4/ Minimum byte programming time excluding system overhead is 16 s (10 s programming +6.0 s write recovery), while maximum is 400 s/byte (16 s x 25 loops allowed by algorithm). Maximum chip programming time is specified lower than the worst case allowed by the programming algorithm since most bytes program significantly faster than the worst case byte.
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3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 41 (see MIL-PRF-38535, appendix A).
3.11 Processing of EEPROMs. All testing requirements and quality assurance provisions herein shall be satisfied by the manufacturer prior to delivery. 3.11.1 Conditions of the supplied devices. Devices will be supplied in an unprogrammed or clear state. No provision will be made for supplying programmed devices. 3.11.2 Erasure of EEPROMs. When specified, devices shall be erased in accordance with procedures and characteristics specified in 4.5.1. 3.11.3 Programming of EEPROMs. When specified, devices shall be programmed in accordance with procedures and characteristics specified in 4.5.2. 3.11.4 Verification of state of EEPROMs. When specified, devices shall be verified as either written to the specified pattern or cleared. As a minimum, verification shall consist of performing a read of the entire array to verify that all bits are in the proper state. Any bit that does not verify to be in the proper state shall constitute a device failure and the device shall be removed from the lot or sample. 3.12 Endurance. A reprogrammability test shall be completed as part of the vendor's reliability monitors. This reprogrammability test shall be done for initial characterization and after any design or process changes which may affect the reprogrammability of the device. The methods and procedures may be vendor specific, but shall guarantee the number of program/erase endurance cycles listed in section 1.3 herein over the full military temperature range. The vendor's procedure shall be kept under document control and shall be made available upon request of the acquiring or preparing activity, along with test data. 3.13 Data retention. A data retention stress test shall be completed as part of the vendor's reliability monitors. This test shall be done for initial characterization and after any design or process change which may affect data retention. The methods and procedures may be vendor specific, but shall guarantee the number of years listed in section 1.3 herein over the full military temperature range. The vendor's procedure shall be kept under document control and shall be made available upon request of the acquiring or preparing activity, along with test data.
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Case T
NOTE: Metric equivalents are given in parenthesis. Symbol Min A A1 A2 A3 .057 .122 .010 .055 .014 .000 .540 .400 .500 .440 .300 .400 .043 0.027 .057 0.033 32 1.09 0.68 .464 11.17 7.62 10.16 1.45 0.84 Typical Inches Max .080 .159 .014 .065 .018 .004 .565 Min 1.45 3.10 0.25 1.38 0.36 0.00 13.72 10.16 12.70 11.79 Reference Millimeters Max 2.03 4.04 0.36 1.65 0.46 0.10 14.35 Reference Solid lid Solid lid Notes
B
CP D D1 D2 E E1 E2 e R N
FIGURE 1. Case outlines.
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Case U
Inches .001 .002 .005 .006 .008 .017 .020 .034
mm 0.03 0.05 0.13 0.15 0.20 0.43 0.51 0.86
Inches mm .040 1.02 .045 1.15 .050 1.27 .132 3.35 .295 7.49 .280 7.11 .410 10.41 .820 20.83
NOTES: 1. Terminal one shall be identified by a mechanical index on the lead or body, or a mark on the top surface within the region shown. 2. Terminal identification numbers need not appear on the package. 3. Weight: 1.5 g maximum. 4. Dimensions are in inches. 5. Metric equivalents are given for general information only. FIGURE 1. Case outlines - Continued.
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Case Z
Inches Symbol A A1 A2 A3 B CP D D1 D2 E E1 E2 e N Min .057 .122 .010 .055 .014 .000
.540
.440 .043
Family: Ceramic leadless chip carrier Millimeters Max Min .080 1.45 .159 3.10 .014 0.25 .065 1.40 .018 0.36 .004 0.00 .670 .400 10.16 .560 13.71 .570 .300 7.62 .460 11.18 .057 1.09 32
Max 2.03 4.04 0.36 1.65 0.46 0.10 17.01 14.22 14.49
Notes Solid lid Solid lid
Reference
Reference 11.68 1.45 Typical
FIGURE 1. Case outlines - Continued.
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Device types Case outlines Terminal number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
All All Terminal symbol VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 DQ7 CE
A10 OE
A11 A9 A8 A13 A14 NC WE
VCC
FIGURE 2. Terminal connections.
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Bus operations CE OE

VIL VIL VIH VIL VIL VIL VIL VIH VIL VIL VIH X 2/ VIL VIL VIL VIH X 2/ VIH WE
VIH VIH X 2/ VIH VIH VIH VIH X 2/ VIL
Pins Read only Read Output disable Standby Auto-select manufacturer code 3/ Auto-select device code 3/ Read/write Read Output disable Standby 8/ Write 1/ 2/ 3/ 4/ 5/ Operation
VPP 1/ VPPL VPPL VPPL VPPL VPPL VPPH VPPH VPPH VPPH
A0 A0 X 2/ X 2/ VIL VIH A0 X 2/ X 2/ A0
A9 A9 X 2/ X 2/ VID 4/ VID 4/ A9 X 2/ X 2/ A9
DQ0 - DQ7 Data out 3-state 3-state 5/ 6/ Data out 7/ 3-state 3-state Data in 9/
Refer to dc characteristics. When VPP = VPPL memory contents can be read but not written or erased. X can be VIL or VIH. Manufacture and device code may also be accessed via a command register write sequence. VID is the auto select high voltage. Refer to dc characteristics. The output for DQ0 - DQ7 shall be as follows:
64
DQ0 - DQ7
DATA = 89H DATA = 01H 6/ The output for DQ0 - DQ7 shall be as follows: DQ0 - DQ7
64
DATA = B4H (device types 01-09, 11-13) DATA = A7H (device types 01-09) DATA = A2H (device types 10-13) 7/ 8/ 9/ Read operations with VPP = VPPH may access array data or the auto select codes. With VPP at high voltage, the standby current equals ICC +IPP (standby). Refer to command definitions for valid Data-In during a write operation.
FIGURE 3. Truth tables.
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Command definitions, device types 01-09 Command BUS cycles required 1 2 2 2 2 2 2 First BUS cycle Operation 1/ Write Write Write Write Write Write Write Address 2/ X X X EA X X X Data 3/ 00H/FFH 90H/80H 20H A0H 40H C0H FFH Second BUS cycle Operation 1/ Read Read Write Read Write Read Write Address 2/ RA IA X X PA X X Data 3/ RD ID 20H EVD PD PVD FFH
Read memory Read auto select codes 4/ Setup erase/erase Erase verify Setup program/program Program verify Reset 5/ 1/ 2/
3/
4/ 5/
Refer to BUS operations for definitions. RA = Address of the memory location to be read. IA = Identifier address: 00H/01H for manufacturer code, 01H/A7H for device code. EA = Address of memory location to be read during erase verify. PA = Address of memory location to be programmed. Address are latched on the falling edge of the write-enable pulse. RD = Data read from location RA during read operation. ID = Data read from location IA during device identification. EVD = Data read from location EA during erase verify. PD = Data to be programmed at location PA. Data is latched on the rising edge of write-enable. PVD = Data read from location PA during program verify. PA is latched on the program command. Following the read Auto Select code ID command, two read operations access manufacturer and device codes. The second bus cycle must be followed by the desired command register write. Command definitions, device types 10-13 Command BUS cycles required 1 3 2 2 2 First BUS cycle Operation 1/ Write Write Write Write Write Address 2/ X X X X X Data 3/ 00H/FFH 80H/90H 30H 10H/50H FFH Second BUS cycle Operation 1/ Read Read Write Write Write Address 2/ RA X PA X Data 3/ RD 30H PD FFH
Read memory Read auto select codes 4/ Embedded erase setup/erase Embedded program setup/program Reset 5/ 1/ 2/ 3/ 4/ 5/
00H/01H 01H/A2H
Refer to BUS operations for definitions. RA = Address of the memory location to be read. PA = Address of memory location to be programmed. Address are latched on the falling edge of the W
pulse.
E RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the rising edge of W E .
Following the read Auto Select code ID command, two read operations access manufacturer and device codes. The second bus cycle must be followed by the desired command register write.
FIGURE 3. Truth tables - Continued.
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AC testing: Inputs are driven at 2.4 V for a logic "1" and 0.45 V for a logic "0". Input pulse rise and fall times are 10 ns.
FIGURE 4. Switching test circuits and waveforms.
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AC waveforms for read operations
FIGURE 4. Switching test circuits and waveforms - Continued.
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4. QUALITY ASSURANCE PROVISIONS 4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. 4.2.1 Additional criteria for device class M. a. b. Delete the sequence specified as initial (preburn-in) electrical parameters through interim (postburn-in) electrical parameters of method 5004 and substitute lines 1 through 6 of table IIA herein. Prior to burn-in, the devices shall be programmed (see 4.5.2 herein) with a checkerboard pattern or equivalent (manufacturers at their option may employ an equivalent pattern provided it is a topologically true alternating bit pattern). The pattern shall be read before and after burn-in. Devices having bits not in the proper state after burn-in shall constitute a device failure and shall be included in the PDA calculation and shall be removed from the lot. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015. (1) d. e. Dynamic burn-in (method 1015 of MIL-STD-883, test condition D; for circuit, see 4.2.1c herein).
c.
Interim and final electrical parameters shall be as specified in table IIA herein. After the completion of all screening, the device shall be erased and verified prior to delivery.
4.2.2 Additional criteria for device classes Q and V. a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with MILPRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015 of MIL-STD-883. Interim and final electrical test parameters shall be as specified in table IIA herein. Additional screening for device class V beyond the requirements of device class Q shall be as specified in appendix B of MIL-PRF-38535 and as detailed in table IIB herein.
b. c.
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). 4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with MIL-PRF38535 including groups A, B, C, D, and E inspections and as specified herein except where option 2 of MIL-PRF-38535 permits alternate in-line control testing. Quality conformance inspection for device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
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TABLE IIA. Electrical test requirements. 1/ 2/ 3/ 4/ 5/ 6/ 7/ Line no. Test requirements Subgroups (per method 5005, table I) Device class M 1 Interim electrical parameters (see 4.2) Static burn-in I method 1015 Same as line 1 Dynamic burn-in (method 1015) Same as line 1 Final electrical parameters Group A test requirements Group C end-point electrical parameters Group D end-point electrical parameters Group E end-point electrical parameters 1*,2,3,7*, 8A,8B,9,10, 11 1*,2,3,7*, 8A,8B,9,10, 11 Required Required Not required Subgroups (per MIL-PRF-38535, table III) Device class Q 1,7,9 or 2,8A,10 Not required Device class V 1,7,9 or 2,8A,10 Not required 1*,7*
2 3 4 5 6

Required 1*,7*
1*,2,3,7*, 8A,8B,9,10, 11 1,2,3,4**,7, 8A,8B,9,10, 11 1,2,3,7, 8A,8B,9,10, 11 2,3,7 8A,8B 1,7,9
7
1,2,3,4**,7,8A, 1,2,3,4**,7, 8A,8B,9,10, 8B,9,10, 11 11 2,8A,10 1,2,3,7 8A,8B 2,3,7 8A,8B 1,7,9
8
9
2,8A,10
10
1,7,9
1/ 2/ 3/ 4/ 5/ 6/ 7/
Blank spaces indicate test are not applicable. Any or all subgroups may be combined when using high-speed testers. Subgroups 7 and 8 functional tests shall verify the truth table. * Indicates PDA applies to subgroups 1 and 7. ** See 4.4.1c. Indicates delta limit (see table IIB) shall be required where specified, and the delta values shall be computed with reference to the previous interim electrical parameters (see line 1). See 4.4.1e.
4.4.1 Group A inspection. a. b. Tests shall be as specified in table IIA herein. Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted.
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c.
Subgroup 4 (CIN and COUT measurements) shall be measured only for initial qualification and after any process or design changes which may affect input or output capacitance. Capacitance shall be measured between the designated terminal and GND at a frequency of 1 MHz. Sample size is 15 devices with no failures and all input and output terminals tested. For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth table. For device classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device; these tests shall have been fault graded in accordance with MIL-STD-883, test method 5012 (see 1.5 herein). O/V (latch-up) tests shall be measured only for initial qualification and after any design or process changes which may affect the performance of the device. For device class M, procedures and circuits shall be maintained under document revision level control by the manufacturer and shall be made available to the preparing activity or acquiring activity upon request. For device classes Q and V, the procedures and circuits shall be under the control of the device manufacturer's TRB in accordance with MIL-PRF-38535 and shall be made available to the preparing activity or acquiring activity upon request. Testing shall be on all pins, on five devices with zero failures. Latch-up test shall be considered destructive. Information contained in JEDEC Standard EIA/JESD78 may be used for reference. All devices selected for testing shall be programmed with a checkerboard pattern or equivalent. After completion of all testing, the devices shall be erased and verified, (except devices submitted for groups B, C, and D testing).
d.
e.
f.
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein. 4.4.2.1 Additional criteria for device class M. a. Steady-state life test conditions, method 1005 of MIL-STD-883: (1) (2) The device selected for testing shall be programmed with a checkerboard pattern. After completion of all testing, the devices shall be erased and verified (except devices submitted for group D testing). Test condition D or E. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005. TA = +125(C, minimum. Test duration: 1,000 hours, except as specified in method 1005 of MIL-STD-883.
(3) (4) b. c.
All devices requiring end-point electrical testing shall be programmed with a checkerboard or equivalent alternating bit pattern. After the completion of all testing, the devices shall be cleared and verified prior to delivery.
4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The test circuit shall be maintained under document revision level control by the device manufacturer's TRB, in accordance with MIL-PRF-38535, and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 of MIL-STD-883. 4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein. The devices selected for testing shall be programmed with a checkerboard pattern. After completion of all testing, the devices shall be erased and verified.
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TABLE IIB. Delta limits at 25(C. Test 1/ Device types All ICCS2 standby ILI ILO 10 percent of specified value in table I. 10 percent of specified value in table I. 10 percent of specified value in table I.
1/ The above parameter shall be recorded before and after the required burn-in and life tests to determine delta. 4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured (see 3.5 herein). RHA levels for device classes M, Q, and V shall be as specified in MIL-PRF-38535. a. b. End-point electrical parameters shall be as specified in table IIA herein. For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All device classes must meet the postirradiation end-point electrical parameter limits as defined in table IA at TA = +25(C 5(C, after exposure, to the subgroups specified in table IIA herein. When specified in the purchase order or contract, a copy of the RHA delta limits shall be supplied.
c.
4.5 Methods of inspection. Methods of inspection shall be as specified in the appropriate figures and tables as follows. 4.5.1 Erasing procedures. The erasing procedures shall be as specified by the device manufacturer and shall be available upon request. 4.5.2 Programming procedure. The programming procedures shall be as specified by the device manufacturer and shall be made available upon request. 4.6 Delta measurements for device class V. Delta measurements, as specified in table IIA, shall be made and recorded before and after the required burn-in screens and steady-state life tests to determine delta compliance. The electrical parameters to be measured, with associated delta limits are listed in table IIB. The device manufacturer may, at his option, either perform delta measurements or within 24 hours after burn-in perform final electrical parameter tests, subgroups 1, 7, and 9. 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor-prepared specification or drawing.
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6.1.2 Substitutability. Device class Q devices will replace device class M devices. 6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the individual documents. This coordination will be accomplished in accordance with MIL-STD-973 using DD Form 1692, Engineering Change Proposal. 6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus when a system application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0525. 6.4 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43216-5000, or telephone (614) 692-0674. 6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in MILPRF-38535, MIL-STD-1331, and as follows: CIN, COUT . . . . . . . . . . . . . . GND . . . . . . . . . . . . . . . . . . . . ICC . . . . . . . . . . . . . . . . . . . . . IIL . . . . . . . . . . . . . . . . . . . . . . IIH . . . . . . . . . . . . . . . . . . . . . TC . . . . . . . . . . . . . . . . . . . . . TA . . . . . . . . . . . . . . . . . . . . . VCC . . . . . . . . . . . . . . . . . . . . VH . . . . . . . . . . . . . . . . . . . . . O/V . . . . . . . . . . . . . . . . . . . . . Input and bidirectional output, terminal-to-GND capacitance. Ground zero voltage potential. Supply current. Input current low. Input current high. Case temperature. Ambient temperature. Positive supply voltage. Output enable and Write enable voltage during chip erase. Latchup over-voltage.
6.5.1 Timing limits. The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time. 6.5.2 Timing parameter abbreviations. All timing abbreviations use lower case characters with upper case subscripts. The initial character is always "t" and is followed by four descriptors. These characters specify two signal points arranged in a "fromto" sequence that define a timing interval. The two descriptors for each signal specify the signal name and the signal transition. Thus the format is: t X
Signal name from which interval is defined Transition direction for first signal Signal name to which interval is defined Transition direction for second signal a. Signal definitions: A = Address D = Data in Q = Data out W = Write enable E = Chip enable G = Output enable b.

X

X

X
Transition definitions: H = Transition to high L = Transition to low V = Transition to valid X = Transition to invalid or don't care Z = Transition to off (high impedance)
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6.5.3 Waveforms.
WAVEFORM SYMBOL
INPUT MUST BE VALID CHANGE FROM H TO L CHANGE FROM L TO H DON'T CARE ANY CHANGE PERMITTED
OUTPUT WILL BE VALID WIIL CHANGE FROM H TO L WILL CHANGE FROM L TO H CHANGING STATE UNKNOWN HIGH IMPEDANCE
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535. The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to this drawing. 6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103. The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by DSCC-VA.
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STANDARD MICROCIRCUIT DRAWING SOURCE APPROVAL BULLETIN DATE: 99-11-16 Approved sources of supply for SMD 5962-90899 are listed below for immediate acquisition only and shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DSCC-VA. This bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML38535. Standard microcircuit drawing PIN 1/ 5962-9089901QXA 5962-9089901MXX 5962-9089901QYA 5962-9089901MYX 5962-9089901MTX 5962-9089901MZX 5962-9089901QUA 5962-9089901MUX 5962-9089902QXA 5962-9089902MXX 5962-9089902QYA 5962-9089902MYX 5962-9089902MTX 5962-9089902MZX 5962-9089902QUA 5962-9089902MUX 5962-9089903QXA 5962-9089903MXX 5962-9089903QYA 5962-9089903MYX 5962-9089903MTX 5962-9089903MZX 5962-9089903QUA 5962-9089903MUX 5962-9089904QXA 5962-9089904MXX 5962-9089904QYA 5962-9089904MYX 5962-9089904MTX 5962-9089904MZX 5962-9089904QUA 5962-9089904MUX Vendor CAGE number 0EU86 3/ 3/ 0EU86 3/ 3/ 3/ 3/ 0EU86 3/ 0EU86 3/ 3/ 0EU86 3/ 3/ 3/ 3/ 0EU86 3/ 0EU86 3/ 3/ 0EU86 3/ 3/ 3/ 3/ 0EU86 3/ 0EU86 3/ 3/ 0EU86 3/ 3/ 3/ 3/ 0EU86 3/ Vendor similar PIN 2/ SMJ28F010B-25JDDM AM28F010-250/BXA MD28F010-25/B SMJ28F010B-25FEM AM28F010-250/BUA MR28F010-25/B MT28F010-25/B MZ28F010-25/B SMJ28F010B-25HKM MF28F010-25/B SMJ28F010B-20JDDM AM28F010-200/BXA MD28F010-20/B SMJ28F010B-20FEM AM28F010-200/BUA MR28F010-20/B MT28F010-20/B MZ28F010-20/B SMJ28F010B-20HKM MF28F010-20/B SMJ28F010B-15JDDM AM28F010-150/BXA MD28F010-15/B SMJ28F010B-15FEM AM28F010-150/BUA MR28F010-15/B MT28F010-15/B MZ28F010-15/B SMJ28F010B-15HKM MF28F010-15/B SMJ28F010B-12JDDM AM28F010-120/BXA MD28F010-12/B SMJ28F010B-12FEM AM28F010-120/BUA MR28F010-12/B MT28F010-12/B MZ28F010-12/B SMJ28F010B-12HKM MF28F010-12/B
See footnotes at end of table.
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STANDARD MICROCIRCUIT DRAWING SOURCE APPROVAL BULLETIN- continued. Standard microcircuit drawing PIN 1/ 5962-9089905QXA 5962-9089905MXX 5962-9089905QYA 5962-9089905MYX 5962-9089905MTX 5962-9089905MZX 5962-9089905QUA 5962-9089905MUX 5962-9089906QXA 5962-9089906MXX 5962-9089906QYA 5962-9089906MYX 5962-9089906MTX 5962-9089906MZX 5962-9089906QUA 5962-9089906MUX 5962-9089907QXA 5962-9089907MXX 5962-9089907QYA 5962-9089907MYX 5962-9089907MTX 5962-9089907MZX 5962-9089907QUA 5962-9089907MUX 5962-9089908QXA 5962-9089908MXX 5962-9089908QYA 5962-9089908MYX 5962-9089908MTX 5962-9089908MZX 5962-9089908QUA 5962-9089908MUX 5962-9089909MXX 5962-9089909MYX 5962-9089909MTX 5962-9089909MZX 5962-9089909MUX 5962-9089910QXA 5962-9089910MXX 5962-9089910QYA 5962-9089910MYX 5962-9089910QUA Vendor CAGE number 0EU86 3/ 3/ 0EU86 3/ 3/ 3/ 3/ 0EU86 3/ 0EU86 3/ 3/ 0EU86 3/ 3/ 3/ 3/ 0EU86 3/ 0EU86 3/ 3/ 0EU86 3/ 3/ 3/ 3/ 0EU86 3/ 0EU86 3/ 3/ 0EU86 3/ 3/ 3/ 3/ 0EU86 3/ 3/ 3/ 3/ 3/ 3/ 0EU86 3/ 0EU86 3/ 0EU86 Vendor similar PIN 2/ SMJ28F010B-25JDDM AM28F010-250C3/BXA MD28F010-25/B SMJ28F010B-25FEM AM28F010-250C3/BUA MR28F010-25/B MT28F010-25/B MZ28F010-25/B SMJ28F010B-25HKM MF28F010-25/B SMJ28F010B-20JDDM AM28F010-200C3/BXA MD28F010-20/B SMJ28F010B-20FEM AM28F010-200C3/BUA MR28F010-20/B MT28F010-20/B MZ28F010-20/B SMJ28F010B-20HKM MF28F010-20/B SMJ28F010B-15JDDM AM28F010-150C3/BXA MD28F010-15/B SMJ28F010B-15FEM AM28F010-150C3/BUA MR28F010-15/B MT28F010-15/B MZ28F010-15/B SMJ28F010B-15HKM MF28F010-15/B SMJ28F010B-12JDDM AM28F010-120C3/BXA MD28F010-12/B SMJ28F010B-12FEM AM28F010-120C3/BUA MR28F010-12/B MT28F010-12/B MZ28F010-12/B SMJ28F010B-12HKM MF28F010-12/B MD28F010-90/B MR28F010-90/B MT28F010-90/B MZ28F010-90/B MF28F010-90/B SMJ28F010B-25JDDM AM28F010A-250/BXA SMJ28F010B-25FEM AM28F010A-250/BUA SMJ28F010B-25HKM
See footnotes at end of table.
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STANDARD MICROCIRCUIT DRAWING SOURCE APPROVAL BULLETIN- continued.
Standard microcircuit drawing PIN 1/ 5962-9089911QXA 5962-9089911QYA 5962-9089911MXX 5962-9089911MYX 5962-9089911QUA 5962-9089912QXA 5962-9089912QYA 5962-9089912MXX 5962-9089912MYX 5962-9089912QUA 5962-9089913QXA 5962-9089913QYA 5962-9089913MXX 5962-9089913MYX 5962-9089913QUA
Vendor CAGE number 0EU86 0EU86 3/ 3/ 0EU86 0EU86 0EU86 3/ 3/ 0EU86 0EU86 0EU86 3/ 3/ 0EU86
Vendor similar PIN 2/ SMJ28F010B-20JDDM SMJ28F010B-20FEM AM28F010A-200/BXA AM28F010A-200/BUA SMJ28F010B-20HKM SMJ28F010B-15JDDM SMJ28F010B-15FEM AM28F010A-150/BXA AM28F010A-150/BUA SMJ28F010B-15HKM SMJ28F010B-12JDDM SMJ28F010B-12FEM AM28F010A-120/BXA AM28F010A-120/BUA SMJ28F010B-12HKM
1/ The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for the part. If the desired lead finish is not listed, contact the Vendor to determine its availability. 2/ Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. 3/ No longer available from an approved source.
Vendor CAGE number 0EU86
Vendor name and address Austin Semiconductor Inc. 8701 Cross Park Drive Austin, TX 78754-4566
Manufacturer code 97
Device code B4H
The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in this information bulletin.
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